1. Field of the Invention
The present invention relates to a stochastic processor and a stochastic computer using the stochastic processor. More particularly, the present invention provides a stochastic computer capable of operating vector matching as an operation essential to an MPEG encoding process or an image recognition process at high speeds by using a stochastic processor configured to carry out stochastic operation.
2. Description of the Related Art
With recent spread of personal computers (PCs), semiconductor devices have been increasingly used at home. In addition to numeric value calculation, personal uses such as Internet, mail, and image processing have been increasing.
However, in the PCs capable of high-speed operations, sufficient speeds are not achieved in all the operations. For example, in order to recognize a voice or speech given off by a person or recognize who a person being viewed through a camera is, enormous amount of operations are required to perform, and therefore, real time processing is difficult.
Basic process of such recognition process is to store data of a voice or face in vector form as reference vector, vectorize input data in the same manner and detect approximation between these data, and perform operation as to which of the reference vectors is closest to the input vector. Such vector comparison process is a basic process used in wide variety of data processing such as associative memory, vector quantization, and pattern recognition such as motion prediction, and data compression.
Such vector comparison requires enormous amount of operations in any of the applications. In Neuman-type computers which are typical of the conventional PCs, in principle, the closest vector cannot be extracted unless comparison operations of all the vectors are finished. As a result, very long time is required.
A novel conventional computer configured to operate “approximation” between plural numeric values (between a set of numeric values and a set of numeric values) is disclosed in “A CMOS Stochastic Associative Processor Using PWM Chaotic Signals” described in IEICE Transactions on Electronics, Vol. E84-C, No. 12, December 2001, pp 1723-1729.
FIG. 23 shows a configuration of the conventional stochastic computer.
The stochastic computer in FIG. 23 is configured to stochastically operate match/mismatch between digital data. When input data 103 matches stored data 103 (both are 1 or 0), 1 is output from a XNOR circuit 120. A PWM chaos generation circuit 121 is connected to an output side of the XNOR circuit 120, and configured to generate pulses whose width varies chaotically. When a latch signal 105 is input to a latch circuit 122 after a lapse of time after the PWM chaos has been generated, the input at this time is held in the latch circuit 122. Since the signal whose width varies chaotically varies is input to the latch circuit 122, an operation in which the value held in the latch circuit 122 becomes High is a stochastic operation. And, when High is held, the switch 109 is turned ON, and thereby allowing current to be supplied by a current source 107. The total sum of these currents is detected and is subjected to a comparison process by an high-order extraction circuit 111. The smaller a distance between the input data 101 and a group of stored data 103 is, the larger the current stochastically detected is, so that approximation between vectors (in this case humming distance) can be stochastically calculated. It should be appreciated that chaos used in the above described prior art uses so-called logistic chaos shown in a mapping map in FIG. 24.
However, in the conventional stochastic computer, some problems exist. First, the conventional stochastic processor is configured to only compare digital data, and therefore, cannot carry out an operation superior to that carried out by a current digital signal processor.
Second, while logistic chaos is used as the chaos, it has not been verified that stochastic operation becomes possible by using the logistic chaos, and therefore, operation reliability of the processor is doubtful.
Third, a width of the chaos or a threshold (latch time) is determined by trial and error. Therefore, how to design and drive the processor is obscure.